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FEATURES
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LTC3614 4A, 4MHz Monolithic Synchronous Step-Down DC/DC Converter DESCRIPTION
The LTC(R)3614 is a low quiescent current monolithic synchronous buck regulator using a current mode, constant frequency architecture. The no-load DC supply current in sleep mode is only 75A while maintaining the output voltage (Burst Mode operation) at no load, dropping to zero current in shutdown. The 2.25V to 5.5V input supply voltage range makes the LTC3614 ideally suited for single Li-Ion as well as fixed low voltage input applications. 100% duty cycle capability provides low dropout operation, extending the operating time in battery-powered systems. The operating frequency is externally programmable up to 4MHz, allowing the use of small surface mount inductors. For switching-noise-sensitive applications, the LTC3614 can be synchronized to an external clock at up to 4MHz. Forced continuous mode operation in the LTC3614 reduces noise and RF interference. Adjustable compensation allows the transient response to be optimized over a wide range of loads and output capacitors. The internal synchronous switch increases efficiency and eliminates the need for an external catch diode, saving external components and board space. The LTC3614 is offered in a leadless 24-pin 3mm x 5mm thermally enhanced QFN package.
L, LT, LTC, LTM, Linear Technology, the Linear logo and Burst Mode are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. Protected by U.S. Patents, including 6580258, 5481178, 5994885, 6304066, 6498466, 6611131.
4A Output Current 2.25V to 5.5V Input Voltage Range Low Output Ripple Burst Mode(R) Operation: IQ = 75A 1% Output Voltage Accuracy Output Voltage Down to 0.6V High Efficiency: Up to 95% Low Dropout Operation: 100% Duty Cycle Programmable Slew Rate on SW Node Reduces Noise and EMI Adjustable Switching Frequency: Up to 4MHz Optional Active Voltage Positioning (AVP) with Internal Compensation Selectable Pulse-Skipping/Forced Continuous/Burst Mode Operation with Adjustable Burst Clamp Programmable Soft-Start Inputs for Start-Up Tracking or External Reference DDR Memory Mode, IOUT = 3A Available in a 24-Pin 3mm x 5mm QFN Thermally Enhanced Package Point-of-Load Supplies Distributed Power Supplies Portable Computer Systems DDR Memory Termination Handheld Devices
APPLICATIONS
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TYPICAL APPLICATION
VIN 2.7V TO 5.5V SVIN PVIN 100 10F 4 EFFICIENCY (%) 90 80 70 60 50 40 30 20 10 0 1 SRLIM/DDR RUN TRACK/SS RT/SYNC LTC3614 SW PGOOD SGND ITH PGND MODE VFB
Efficiency and Power Loss vs Load Current
1 POWER LOSS (W)
330nH
VOUT 2.5V 4A 47F 2
0.1
0.01
665k
3614 TA01a
210k
VOUT = 2.5V
VIN = 2.8V VIN = 3.3V VIN = 5V
0
10 100 1000 OUTPUT CURRENT (mA)
10000
3614 TA01b
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LTC3614 ABSOLUTE MAXIMUM RATINGS
(Note 1)
PIN CONFIGURATION
TOP VIEW TRACK/SS MODE 20 PGOOD 19 RUN 18 SVIN 25 PGND 17 PVIN 16 SW 15 SW 14 SW 13 SW 9 NC 10 11 12 PVIN PVIN NC
PVIN, SVIN Voltages...................................... -0.3V to 6V SW Voltage ..................................-0.3V to (PVIN + 0.3V) ITH, RT/SYNC Voltages ............... -0.3V to (SVIN + 0.3V) SRLIM, TRACK/SS Voltages ....... -0.3V to (SVIN + 0.3V) MODE, RUN, VFB Voltages .......... -0.3V to (SVIN + 0.3V) PGOOD Voltage ............................................ -0.3V to 6V Operating Junction Temperature Range (Notes 2, 11) .......................................... -40C to 125C Storage Temperature.............................. -65C to 150C
24 23 22 21 SRLIM/DDR 1 RT/SYNC 2 SGND 3 PVIN 4 SW 5 SW 6 SW 7 SW 8
UDD PACKAGE 24-LEAD (3mm 5mm) PLASTIC QFN TJMAX = 125C, JA = 38C/W EXPOSED PAD (PIN 25) IS PGND, MUST BE SOLDERED TO PCB
ORDER INFORMATION
LEAD FREE FINISH LTC3614EUDD#PBF LTC3614IUDD#PBF TAPE AND REEL LTC3614EUDD#TRPBF LTC3614IUDD#TRPBF PART MARKING* LFVM LFVM PACKAGE DESCRIPTION 24-Lead (3mm x 5mm) Plastic QFN 24-Lead (3mm x 5mm) Plastic QFN TEMPERATURE RANGE -40C to 125C -40C to 125C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. Consult LTC Marketing for information on non-standard lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
VFB
ITH
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LTC3614 ELECTRICAL CHARACTERISTICS
SYMBOL VIN VUVLO VFB PARAMETER Operating Voltage Range Undervoltage Lockout Threshold Feedback Voltage Internal Reference SVIN Ramping Down SVIN Ramping Up (Note 3) VTRACK = SVIN, VDDR = 0V 0C < TJ < 85C -40C < TJ < 125C (Note 3) VTRACK = 0.3V, VDDR = SVIN (Note 3) VTRACK = 0.5V, VDDR = SVIN VFB = 0.6V SVIN = PVIN = 2.25V to 5.5V (Notes 3, 4) TRACK/SS = SVIN ITH from 0.5V to 0.9V (Notes 3, 4) VITH = SVIN (Note 5) VFB = 0.5V, VMODE = SVIN (Note 6) VFB = 0.7V, VMODE = 0V, ITH = SVIN (Note 5) VFB = 0.7V, VMODE = 0V (Note 4) Shutdown Current RDS(ON) ILIM Top Switch On-Resistance Bottom Switch On-Resistance Top Switch Current Limit SVIN = PVIN = 5.5V, VRUN = 0V PVIN = 3.3V (Note 10) PVIN = 3.3V (Note 10) Sourcing (Note 8), VFB = 0.5V Duty Cycle <35% Duty Cycle = 100% Sinking (Note 8), VFB = 0.7V, Forced Continuous Mode -5A < IITH < 5A (Note 4) (Note 4) VFB from 0.06V to 0.54V, TRACK/SS = SVIN (Note 7 ) 0.65 0.62 60 200 RT/SYNC = 370k VRT/SYNC = SVIN
l l l l
The l denotes the specifications which apply over the full operating junction temperature range, otherwise specifications are at TA TJ = 25C. VIN = 3.3V, RT/SYNC = SVIN unless otherwise specified (Notes 1, 2, 11).
CONDITIONS
l l l
MIN 2.25 1.7
TYP
MAX 5.5 2.25
UNITS V V V V V V V nA %/V % % A A A A m m
l
0.594 0.591 0.288 0.488
0.6 0.300 0.500
0.606 0.609 0.312 0.512 30 0.2 0.25 2.6
Feedback Voltage External Reference (Note 7) IFB VLINEREG VLOADREG IS Feedback Input Current Line Regulation Load Regulation Active Mode Supply Current Sleep Mode Supply Current
1100 75 130 0.1 35 25 7.5 5.3 -6 9 -8 200 30 1.2 1.9 10.5 -11 100 175 1
A A A S A ms V s MHz MHz MHz V V A V V V V V
3614f
Bottom Switch Current Limit gm(EA) IEAO tSS VTRACK/SS tTRACK/SS_DIS Error Amplifier Transconductance Error Amplifier Maximum Output Current Internal Soft-Start Time Enable Internal Soft-Start Soft-Start Discharge Time at Start-Up
RON(TRACK/SS_DIS) TRACK/SS Pull-Down Resistor at Start-Up fOSC fSYNC VRT/SYNC ISW(LKG) VDDR VMODE (Note 9) Oscillator Frequency Internal Oscillator Frequency Synchronization Frequency Range SYNC Input Threshold High SYNC Input Threshold Low Switch Leakage Current DDR Option Enable Voltage Internal Burst Mode Operation Pulse-Skipping Mode Forced Continuous Mode External Burst Mode Operation SVIN - 0.3 1.1 0.45 SVIN = PVIN = 5.5V, VRUN = 0V SVIN - 0.3 0.8 1.8 0.3 1.2 . 0.1 1 2.25
1.2 2.7 4 0.3 1 0.3 SVIN * 0.58 0.8
3
LTC3614 ELECTRICAL CHARACTERISTICS
SYMBOL PGOOD PARAMETER Power Good Voltage Windows
The l denotes the specifications which apply over the full operating junction temperature range, otherwise specifications are at TA TJ = 25C. VIN = 3.3V, RT/SYNC = SVIN unless otherwise specified (Notes 1, 2, 11).
CONDITIONS TRACK/SS = SVIN, Entering Window VFB Ramping Up VFB Ramping Down TRACK/SS = SVIN, Leaving Window VFB Ramping Up VFB Ramping Down MIN -3 3 TYP -6 6 9 -9 70 8 Input High Input Low
l l
MAX
UNITS % %
11 -11 140 33 0.4
% % s V V
tPGOOD RPGOOD VRUN
Power Good Blanking Time Power Good Pull-Down On-Resistance RUN voltage
Entering and Leaving Window
105 17
1
Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: The LTC3614E is guaranteed to meet performance specifications over the 0C to 85C operating junction temperature range. Specifications over the -40C to 125C operating junction temperature range are assured by design, characterization and correlation with statistical process controls. The LTC3614I is guaranteed to meet specifications over the full -40C to 125C operating junction temperature range. Note that the maximum ambient temperature is determined by specific operating conditions in conjunction with board layout, the rated package thermal resistance and other environmental factors. Note 3: This parameter is tested in a feedback loop which servos VFB to the midpoint for the error amplifier (VITH = 0.75V). Note 4: External compensation on ITH pin.
Note 5: Tying the ITH pin to SVIN enables the internal compensation and AVP mode. Note 6: Dynamic supply current is higher due to the internal gate charge being delivered at the switching frequency. Note 7: See description of the TRACK/SS pin in the Pin Functions section. Note 8: In sourcing mode the average output current is flowing out of the SW pin. In sinking mode the average output current is flowing into the SW Pin. Note 9: See description of the MODE pin in the Pin Functions section. Note 10: Guaranteed by correlation and design to wafer level measurements for QFN packages. Note 11: This IC includes overtemperature protection that is intended to protect the device during momentary overload conditions. Junction temperature will exceed 125C when overtemperature protection is active. Continuous operation above the specified maximum operating junction temperature may impair device reliability.
TYPICAL PERFORMANCE CHARACTERISTICS VIN = 3.3V, RT/SYNC = SVIN unless otherwise noted.
Efficiency vs Load Current Burst Mode Operation (VMODE = 0V)
100 90 80 EFFICIENCY (%) EFFICIENCY (%) 70 60 50 40 30 20 10 0 1 VIN = 2.5V VIN = 3.3V VIN = 5V 10 100 1000 OUTPUT CURRENT (mA) 10000
3614 G01
Efficiency vs Load Current Burst Mode Operation (VMODE = 0V)
100 90 80 EFFICIENCY (%) 70 60 50 40 30 20 10 0 1 VIN = 2.5V VIN = 3.3V VIN = 5V 10 100 1000 OUTPUT CURRENT (mA) 10000
3614 G02
Efficiency vs Load Current
100 90 80 70 60 50 40 30 20 10 0 1 Burst Mode OPERATION PULSE-SKIPPING FORCED CONTINUOUS 10 100 1000 OUTPUT CURRENT (mA) 10000
3614 G03
VOUT = 1.8V
VOUT = 1.2V
VOUT = 1.8V
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LTC3614 TYPICAL PERFORMANCE CHARACTERISTICS VIN = 3.3V, RT/SYNC = SVIN unless otherwise noted.
Efficiency vs Input Voltage Burst Mode Operation (VMODE = 0V)
100 90 80 EFFICIENCY (%) 70 60 50 40 30 IOUT = 6mA IOUT = 600mA IOUT = 2A 2.5 3 3.5 4 4.5 INPUT VOLTAGE (V) 5 5.5
3614 G04
Efficiency vs Frequency Burst Mode Operation (VMODE = 0V), IOUT = 2A
95 94 93 92 91 90 89 88 87 86 85 84 83 82 0.5 VIN = 3.3V VOUT = 1.8V 1.5 1.3 1.1 VOUT ERROR (%) 0.9 0.7 0.5 0.3 0.1 -0.1 -0.3
Load Regulation (VOUT = 1.8V)
FORCED CONTINUOUS MODE PULSE-SKIPPING MODE INTERNAL Burst Mode OPERATION
VOUT = 1.8V
EFFICIENCY (%)
150nH 330nH 470nH 1 1.5 2 2.5 3 3.5 FREQUENCY (MHz) 4 4.5
0
2000 3000 1000 OUTPUT CURRENT (mA)
4000
3614 G06
3614 G05
Line Regulation
0.3 0.2 VOUT ERROR (%) 0.1 0 VOUT 20mV/DIV
Burst Mode Operation
Pulse-Skipping Mode Operation
VOUT 20mV/DIV
-0.1 IL 1A/DIV 2.75 3.30 3.85 4.40 INPUT VOLTAGE (V) 4.95 5.50 VOUT = 1.8V IOUT = 150mA VMODE = 0V 20s/DIV
3614 G08
-0.2 -0.3 2.20
IL 1A/DIV VOUT = 1.8V IOUT = 150mA VMODE = 3.3V 20s/DIV
3614 G09
3614 G07
Forced Continuous Mode Operation
VOUT 20mV/DIV
Load Step Transient in Pulse-Skipping Mode
Load Step Transient in Burst Mode Operation
VOUT 100mV/DIV
VOUT 100mV/DIV
IL 500mA/DIV
ILOAD 2A/DIV VOUT = 1.8V IOUT = 100mA VMODE = 1.5V 1s/DIV
3614 G10
ILOAD 2A/DIV 100s/DIV VOUT = 1.8V ILOAD = 100mA TO 4A VMODE = 3.3V COMPENSATION FIGURE 1
3614 G11
100s/DIV VOUT = 1.8V ILOAD = 100mA TO 4A VMODE = 0V COMPENSATION FIGURE 1
3614 G12
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LTC3614 TYPICAL PERFORMANCE CHARACTERISTICS VIN = 3.3V, RT/SYNC = SVIN unless otherwise noted.
Load Step Transient in Forced Continuous Mode without AVP Mode Load Step Transient in Forced Continuous Mode with AVP Mode Load Step Transient in Forced Continuous Mode Sourcing and Sinking Current
VOUT 100mV/DIV
VOUT 100mV/DIV
VOUT 200mV/DIV
ILOAD 2A/DIV 100s/DIV VOUT = 1.8V ILOAD = 100mA TO 4A, VMODE = 1.5V COMPENSATION FIGURE 1
3614 G13
ILOAD 2A/DIV 100s/DIV VOUT = 1.8V ILOAD = 100mA TO 4A, VMODE = 1.5V
3614 G14
ILOAD 2A/DIV 100s/DIV VOUT = 1.8V ILOAD = -3A TO 3A, VMODE = 1.5V COMPENSATION FIGURE 1
3614 G15
Sinking Current
VOUT 100mV/DIV RUN 10V/DIV PGOOD 10V/DIV SW 2V/DIV VOUT 500mV/DIV
Internal Start-Up in Forced Continuous Mode
Tracking Up/Down in Forced Continuous Mode, Non DDR Mode
VOUT 1V/DIV
VTRACK/SS 500mV/DIV
IL 2A/DIV
IL 2A/DIV
PGOOD 2V/DIV 500s/DIV VOUT = 1.8V IOUT = 0A, VMODE = 1.5V
3614 G17
1s/DIV VOUT = 1.8V IOUT = -3A, VMODE = 1.5V
3614 G16
2ms/DIV VOUT = 0V TO 1.8V IOUT = 3A, VTRACK/SS = 0V TO 0.7V VMODE = 1.5V, VSRLIM/DDR = 0V
3614 G18
Tracking Up/Down in Forced Continuous Mode, DDR Pin Tied to SVIN
0.606 0.604 VOUT 500mV/DIV REFERENCE VOLTAGE (V) 0.602
Reference Voltage vs Temperature
0.05
Switch On-Resistance vs Input Voltage
0.04 MAIN SWITCH RDS(0N) () 0.03 SYNCHRONOUS SWITCH 0.02
0.600 0.598 0.596 0.594 -50 -30 -10 10 30 50 70 90 110 130 TEMPERATURE (C)
3614 G20
VTRACK/SS 200mV/DIV
PGOOD 2V/DIV 2ms/DIV VOUT = 0V TO 1.2V IOUT = 3A, VTRACK/SS = 0V TO 0.4V VMODE = 1.5V, VSRLIM/DDR = 3.3V
3614 G19
0.01
0
2.5
3.0
4.0 4.5 3.5 INPUT VOLTAGE (V)
5.0
5.5
3614 G21
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LTC3614 TYPICAL PERFORMANCE CHARACTERISTICS VIN = 3.3V, RT/SYNC = SVIN unless otherwise noted.
Switch On-Resistance vs Temperature
0.045 0.040 0.035 0.030 RDS(ON) () 0.025 0.020 0.015 0.010 0.005 0 -50 -30 -10 10 30 50 70 90 110 130 TEMPERATURE (C)
3614 G22
Frequency vs Resistor on RT/SYNC Pin
4500 0.8 0.6 FREQUENCY VARIATION (%) 0 200 400 600 800 1000 1200 1400 RESISTOR ON RT/SYNC PIN (k)
3614 G23
Frequency vs Temperature
MAIN SWITCH FREQUENCY (kHz)
4000 3500 3000 2500 2000 1500 1000 500 0
0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 -1.2 -50 -30 -10 10 30 50 70 90 100 130 TEMPERATURE (C)
3614 G24
SYNCHRONOUS SWITCH
Frequency vs Input Voltage
1.0 0.5 FREQUENCY VARIATION (%) SWITCH LEAKAGE (nA) 0 -0.5 -1.0 -1.5 -2.0 -2.5 2.25 8000 7000 6000 5000 4000 3000 2000 1000 2.75 3.25 3.75 4.25 4.75 INPUT VOLTAGE (V) 5.25
3614 G25
Switch Leakage vs Temperature, Main Switch
VIN = 2.25V VIN = 3.3V VIN = 5.5V SWITCH LEAKAGE (nA) 8000 7000 6000 5000 4000 3000 2000 1000
Switch Leakage vs Temperature, Synchronous Switch
VIN = 2.25V VIN = 3.3V VIN = 5.5V
0 -50 -30 -10 10 30 50 70 90 110 130 TEMPERATURE (C)
3614 G26
0 -50 -30 -10 10 30 50 70 90 110 130 TEMPERATURE (C)
3614 G27
Dynamic Supply Current vs Input Voltage without AVP Mode
100 DYNAMIC SUPPLY CURRENT (mA) FREQ = 2.25MHz FORCED CONTINUOUS MODE 10 DYNAMIC SUPPLY CURRENT (mA) 100
Dynamic Supply Current vs Temperature without AVP Mode
FREQ = 2.25MHz FORCED CONTINUOUS MODE VOUT 500mV/DIV PULSE-SKIPPING MODE IL 5A/DIV Burst Mode OPERATION 0.1
VOUT Short to GND, Forced Continuous Mode
10
1
PULSE-SKIPPING MODE
1
Burst Mode OPERATION 0.1
0.01 2.25
2.75
3.25 3.75 4.25 4.75 INPUT VOLTAGE (V)
5.25
3614 G28
0.01 -50 -30 -10 10 30 50 70 90 110 130 TEMPERATURE (C)
3614 G29
VOUT = 1.8V IOUT = 0A VMODE = 1.5V
100s/DIV
3614 G30
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LTC3614 TYPICAL PERFORMANCE CHARACTERISTICS VIN = 3.3V, RT/SYNC = SVIN unless otherwise noted.
Start-Up from Shutdown with Prebiased Output (Overvoltage) (Forced Continuous Mode)
1.88 PGOOD 5V/DIV VOUT 500mV/DIV VOUT (V) 1.86 1.84 1.82 1.80 -3A, 2MHz, 25C IL 5A/DIV 1.78 1.76 50s/DIV PREBIASED VOUT = 2.2V VOUT = 1.2V, IOUT = 0A VMODE = 1.5V
3614 G31
Output Voltage During Sinking vs Input Voltage (VOUT = 1.8V, 0.47H Inductor)
-3A, 2MHz, 120C
1.74 2.25
2.75
3.25 4 4.5 INPUT VOLTAGE (V)
5.25
3614 G32
PIN FUNCTIONS
SRLIM/DDR (Pin 1): Slew Rate Limit. Tying this pin to ground selects maximum slew rate. Minimum slew rate is selected when the pin is open. Connecting a resistor from SRLIM/DDR to ground allows the slew rate to be continuously adjusted. If SRLIM/DDR is tied to SVIN, DDR mode is selected. In DDR mode the slew rate limit is set to maximum. RT/SYNC (Pin 2): Oscillator Frequency. This pin provides three ways of setting the constant switching frequency: 1. Connecting a resistor from RT/SYNC to ground will set the switching frequency based on the resistor value. 2. Driving the RT/SYNC pin with an external clock signal will synchronize the LTC3614 to the applied frequency. The slope compensation is automatically adapted to the external clock frequency. 3. Tying the RT/SYNC pin to SVIN enables the internal 2.25MHz oscillator frequency. SGND (Pin 3): Signal Ground. All small-signal and compensation components should connect to this ground, which in turn should connect to PGND at a single point. PVIN (Pins 4, 10, 11, 17): Power Input Supply. PVIN connects to the source of the internal P-channel power MOSFET. This pin is independent of SVIN and may be connected to the same voltage or to a lower voltage supply. SW (Pins 5, 6, 7, 8, 13, 14, 15, 16): Switch Node. Connection to the inductor. These pins connect to the drains of the internal power MOSFET switches. NC (Pins 9, 12): Can be connected to ground or left open. SVIN (Pin 18): Signal Input Supply. This pin powers the internal control circuitry and is monitored by the undervoltage lockout comparator.
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LTC3614 PIN FUNCTIONS
RUN (Pin 19): Enable Pin. Forcing this pin to ground shuts down the LTC3614. In shutdown, all functions are disabled and the chip draws <1A of supply current. PGOOD (Pin 20): Power Good. This open-drain output is pulled down to SGND on start-up and while the FB voltage is outside the power good voltage window. If the FB voltage increases and stays inside the power good window for more than 100s the PGOOD pin is released. If the FB voltage leaves the power good window for more than 100s the PGOOD pin is pulled down. In DDR mode (DDR = VIN), the power good window moves in relation to the actual TRACK/SS pin voltage. During up/ down tracking the PGOOD pin is always pulled down. In shutdown the PGOOD output will actively pull down and may be used to discharge the output capacitors via an external resistor. MODE (Pin 21): Mode Selection. Tying the MODE pin to SVIN or SGND enables pulse-skipping mode or Burst Mode operation (with an internal Burst Mode clamp), respectively. If this pin is held at slightly higher than half of SVIN, forced continuous mode is selected. Connecting this pin to an external voltage between 0.45V and 0.8V selects Burst Mode operation with the burst clamp set to the pin voltage. See the Operation section for more details. VFB (Pin 22): Voltage Feedback Input Pin. Senses the feedback voltage from the external resistive divider across the output. ITH (Pin 23): Error Amplifier Compensation. The current comparator's threshold increases with this control voltage. Tying this pin to SVIN enables internal compensation and AVP mode. TRACK/SS (Pin 24): Track/External Soft-Start/External Reference. Start-up behavior is programmable with the TRACK/SS pin: 1. Tying this pin to SVIN selects the internal soft-start circuit. 2. External soft-start timing can be programmed with a capacitor to ground and a resistor to SVIN. 3. TRACK/SS can be used to force the LTC3614 to track the start-up behavior of another supply. The pin can also be used as external reference input. See the Applications Information section for more information. PGND (Exposed Pad Pin 25): Power Ground. This pin connects to the source of the internal N-channel power MOSFET. This pin should be connected close to the (-) terminal of CIN and COUT.
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LTC3614 FUNCTIONAL BLOCK DIAGRAM
SVIN SGND RT/SYNC ITH ITH SENSE COMPARATOR PVIN PVIN PVIN PVIN
RUN
BANDGAP AND BIAS
+
OSCILLATOR SVIN - 0.3V INTERNAL COMPENSATION CURRENT SENSE
-
R
ITH LIMIT FOLDBACK AMPLIFIER
PMOS CURRENT COMPARATOR
0.3V
0.6V
VFB
- +
MODE
TRACK/SS
SOFT-START
0.555V
+ - +
LOGIC
0.645V PGOOD
-
10
+
-
+
-
+ +
-
ERROR AMPLIFIER
+ -
SLOPE COMPENSATION
BURST COMPARATOR SLEEP DRIVER SW SW SW SW SW SW SW SW REVERSE COMPARATOR IREV
+ -
PGND
EXPOSED PAD SRLIM/DDR MODE
3614 BD
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LTC3614 OPERATION
Main Control Loop The LTC3614 is a monolithic, constant frequency, current mode step-down DC/DC converter. During normal operation, the internal top power switch (P-channel MOSFET) is turned on at the beginning of each clock cycle. Current in the inductor increases until the current comparator trips and turns off the top power switch. The peak inductor current at which the current comparator trips is controlled by the voltage on the ITH pin. The error amplifier adjusts the voltage on the ITH pin by comparing the feedback signal from a resistor divider on the VFB pin with an internal 0.6V reference. When the load current increases, it causes a reduction in the feedback voltage relative to the reference. The error amplifier raises the ITH voltage until the average inductor current matches the new load current. Typical voltage range for the ITH pin is from 0.1V to 0.9V with 0.45V corresponding to zero current. When the top power switch shuts off, the synchronous power switch (N-channel MOSFET) turns on until either the bottom current limit is reached or the next clock cycle begins. The bottom current limit is typically set at -8A for forced continuous mode and 0A for Burst Mode operation and pulse-skipping mode. The operating frequency defaults to 2.25MHz when RT/SYNC is connected to SVIN, or can be set by an external resistor connected between the RT/SYNC pin and ground, or by a clock signal applied to the RT/SYNC pin. The switching frequency can be set from 300kHz to 4MHz. Overvoltage and undervoltage comparators pull the PGOOD output low if the output voltage varies more than 7.5% (typical) from the set point. Mode Selection The MODE pin is used to select one of four different operating modes:
Mode Selection Voltage
SVIN SVIN - 0.3V SVIN * 0.58 PS PULSE-SKIPPING MODE ENABLE
FC 1.1V 0.8V 0.45V 0.3V SGND
FORCED CONTINUOUS MODE ENABLE
BM EXT BM
3614 OP01
Burst Mode ENABLE--EXTERNAL CLAMP , CONTROLLED BY VOLTAGE APPLIED AT MODE PIN Burst Mode ENABLE--INTERNAL CLAMP
Burst Mode Operation--Internal Clamp Connecting the MODE pin to SGND enables Burst Mode operation with an internal clamp. In Burst Mode operation the internal power switches operate intermittently at light loads. This increases efficiency by minimizing switching losses. During the intervals when the switches are idle, the LTC3614 enters sleep state where many of the internal circuits are disabled to save power. During Burst Mode operation, the minimum peak inductor current is internally clamped and the voltage on the ITH pin is monitored by the burst comparator to determine when sleep mode is enabled and disabled. When the average inductor current is greater than the load current, the voltage on the ITH pin drops. As the ITH voltage falls below the internal clamp, the burst comparator trips and enables sleep mode. During sleep mode, both power MOSFETs are held off and the load current is solely supplied by the output capacitor. When the output voltage drops, the top power switch is turned back on and the internal circuits are re-enabled. This process repeats at a rate that is dependent on the load current.
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LTC3614 OPERATION
Burst Mode Operation--External Clamp Connecting the MODE pin to a voltage in the range of 0.45V to 0.8V enables Burst Mode operation with external clamp. During this mode of operation the minimum voltage on the ITH pin is externally set by the voltage on the MODE pin. It is recommended to use Burst Mode operation with internal burst clamp for temperatures above 85C ambient. Pulse-Skipping Mode Operation Pulse-skipping mode is similar to Burst Mode operation, but the LTC3614 does not disable power to the internal circuitry during sleep mode. This improves output voltage ripple but uses more quiescent current, compromising light load efficiency. Tying the MODE pin to SVIN enables pulse-skipping mode. As the load current decreases, the peak inductor current will be determined by the voltage on the ITH pin until the ITH voltage drops below the voltage level corresponding to 0A. At this point, the peak inductor current is determined by the minimum on-time of the current comparator. If the load demand is less than the average of the minimum ontime inductor current, switching cycles will be skipped to keep the output voltage in regulation. Forced Continuous Mode In forced continuous mode the inductor current is constantly cycled which creates a minimum output voltage ripple at all output current levels. Connecting the MODE pin to a voltage in the range of 1.1V to SVIN * 0.58 will enable forced continuous mode operation. At light loads, forced continuous mode operation is less efficient than Burst Mode or pulse-skipping operation, but may be desirable in some applications where it is necessary to keep switching harmonics out of the signal band. Forced continuous mode must be used if the output is required to sink current. Low Supply Operation The LTC3614 is designed to operate down to an input supply voltage of 2.25V. An important consideration at low input supply voltages is that the RDS(ON) of the P-channel and N-channel power switches increases. The user should calculate the power dissipation when the LTC3614 is used at 100% duty cycle with low input voltages to ensure that thermal limits are not exceeded. See the Typical Performance Characteristics graphs. Short-Circuit Protection The peak inductor current at which the current comparator shuts off the top power switch is controlled by the voltage on the ITH pin. If the output current increases, the error amplifier raises the ITH pin voltage until the average inductor current matches the new load current. In normal operation the LTC3614 clamps the maximum ITH pin voltage at approximately 0.9V which corresponds typically to 9A peak inductor current. When the output is shorted to ground, the inductor current decays very slowly during a single switching cycle. The LTC3614 uses two techniques to prevent current runaway from occurring. Dropout Operation As the input supply voltage approaches the output voltage, the duty cycle increases toward the maximum on-time. Further reduction of the supply voltage forces the main switch to remain on for more than one cycle, eventually reaching 100% duty cycle. The output voltage will then be determined by the input voltage minus the voltage drop across the internal P-channel MOSFET and the inductor.
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LTC3614 OPERATION
If the output voltage drops below 50% of its nominal value, the clamp voltage at ITH pin is lowered causing the maximum peak inductor current to decrease gradually with the output voltage. When the output voltage reaches 0V the clamp voltage at the ITH pin drops to 40% of the clamp voltage during normal operation. The short-circuit peak inductor current is determined by the minimum on-time of the LTC3614, the input voltage and the inductor value. This foldback behavior helps in limiting the peak inductor current when the output is shorted to ground. It is disabled during internal or external soft-start and tracking up/down operation (see the Applications Information section). A secondary limit is also imposed on the valley inductor current. If the inductor current measured through the bottom MOSFET increases beyond 12A typical, the top power MOSFET will be held off and switching cycles will be skipped until the inductor current is reduced.
APPLICATIONS INFORMATION
The basic LTC3614 application circuit is shown in Figure 1. Operating Frequency Selection of the operating frequency is a trade-off between efficiency and component size. High frequency operation allows the use of smaller inductor and capacitor values. Operation at lower frequencies improves efficiency by reducing internal gate charge losses but requires larger inductance values and/or capacitance to maintain low output ripple voltage. The operating frequency of the LTC3614 is determined by an external resistor that is connected between the RT/SYNC pin and ground. The value of the resistor sets
VIN 2.25V TO 5.5V RSS 2M PVIN SVIN RUN TRACK/SS SRLIM/DDR RT/SYNC LTC3614 SW PGOOD SGND ITH PGND MODE VFB R2 196k
the ramp current that is used to charge and discharge an internal timing capacitor within the oscillator and can be calculated by using the following equation: RT = 3.82 * 1011Hz - 16k fOSC (Hz )
Although frequencies as high as 4MHz are possible, the minimum on-time of the LTC3614 imposes a minimum limit on the operating duty cycle. The minimum on-time is typically 60ns; therefore, the minimum duty cycle is equal to 60ns * fOSC(Hz)*100%. Tying the RT/SYNC pin to SVIN sets the default internal operating frequency to 2.25MHz 20%.
CIN1 10F 4 L1 330nH
CSS 22nF RC 15k CC 470pF
RT 130k CC1 10pF (OPT)
VOUT 1.8V COUT2 4A 100F
R1 392k
3614 F01
Figure 1. 1.8V, 4A Step-Down Regulator
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LTC3614 APPLICATIONS INFORMATION
Frequency Synchronization The LTC3614's internal oscillator can be synchronized to an external frequency by applying a square wave clock signal to the RT/SYNC pin. During synchronization, the top switch turn-on is locked to the falling edge of the external frequency source. The synchronization frequency range is 300kHz to 4MHz. During synchronization all operation modes can be selected. It is recommended that the regulator is powered down (RUN pin to ground) before removing the clock signal on the RT/SYNC pin in order to reduce inductor current ripple. AC coupling should be used if the external clock generator cannot provide a continuous clock signal throughout start-up, operation and shutdown of the LTC3614. The size of capacitor CSYNC depends on parasitic capacitance on the RT/SYNC pin and is typically in the range of 10pF to 22pF .
VIN LTC3614 SVIN RT/SYNC
Inductor Selection For a given input and output voltage, the inductor value and operating frequency determine the ripple current. The ripple current IL increases with higher VIN and decreases with higher inductance: V V IL = OUT * 1- OUT VIN fSW * L Having a lower ripple current reduces the core losses in the inductor, the ESR losses in the output capacitors and the output voltage ripple. A reasonable starting point for selecting the ripple current is IL = 0.3 * IOUT(MAX). The largest ripple current occurs at the highest VIN. To guarantee that the ripple current stays below a specified maximum, the inductor value should be chosen according to the following equation: VOUT VOUT L= * 1- V fSW * IL(MAX) IN(MAX) The inductor value will also have an effect on Burst Mode operation. The transition to low current operation begins when the peak inductor current falls below a level set by the burst clamp. Lower inductor values result in higher ripple current which causes this to occur at lower load currents. This causes a dip in efficiency in the upper range of low current operation. In Burst Mode operation, lower inductance values will cause the burst frequency to increase. Inductor Core Selection Once the value for L is known, the type of inductor must be selected. Actual core loss is independent of core size for fixed inductor value, but it is very dependent on the inductance selected. As the inductance increases, core losses decrease. Unfortunately, increased inductance requires more turns of wire and therefore, copper losses will increase.
fOSC 2.25MHz
VIN 0.4V RT
LTC3614 SVIN RT/SYNC SGND
fOSC 1/RT
VIN
LTC3614 SVIN RT/SYNC SGND 1.2V 0.3V
fOSC 1/TP
TP VIN CSYNC
LTC3614 SVIN RT/SYNC SGND
fOSC 1/TP
RT
3614 F02
Figure 2. Setting the Switching Frequency
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LTC3614 APPLICATIONS INFORMATION
Ferrite designs have very low core losses and are preferred at high switching frequencies, so design goals can concentrate on copper loss and preventing saturation. Ferrite core material saturates "hard," meaning that inductance collapses abruptly when the peak design current is exceeded. This results in an abrupt increase in inductor ripple current and consequently output voltage ripple. Do not allow a ferrite core to saturate! Different core materials and shapes will change the size/current and price/current relationship of an inductor. Toroid or shielded pot cores in ferrite or permalloy materials are small and don't radiate much energy, but generally cost more than powdered iron core inductors with similar characteristics. The choice of which style inductor to use mainly depends on the price versus size requirements and any radiated field/EMI requirements. Table 1 shows some typical surface mount inductors that work well in LTC3614 applications. Input Capacitor (CIN) Selection In continuous mode, the source current of the top P-channel MOSFET is a square wave of duty cycle VOUT/VIN. To prevent large input voltage transients, a low ESR capacitor sized for the maximum RMS current must be used at VIN. The maximum RMS capacitor current is given by: V V IRMS =IOUT(MAX) * OUT * IN - 1 VIN VOUT This formula has a maximum at VIN = 2VOUT , where IRMS = IOUT/2. This simple worst-case condition is commonly used for design because even significant deviations do not offer much relief. Note that ripple current ratings from capacitor manufacturers are often based on only 2000 hours of life which makes it advisable to further derate the capacitor, or choose a capacitor rated at a higher temperature than required. Several capacitors may also be paralleled to meet size or height requirements in the design.
Table 1. Representative Surface Mount Inductors
INDUCTANCE (H) 0.10 0.15 0.20 0.22 0.33 0.47 0.2 0.3 0.47 0.22 0.47 0.68 0.25 0.47 0.100 0.188 0.272 0.350 0.400 DCR (m) 1.5 1.9 2.4 2.5 3.5 4 2.5 3.2 4.2 2.8 4.2 5.5 2.5 3.4 0.123 0.100 0.100 0.100 0.100 SATURATION CURRENT (A) 60 52 41 40 30 26 21.7 15.4 13.6 23 17 15 18 16 20 21 14 11 8 DIMENSIONS (mm) 6.5 x 6.9 6.5 x 6.9 6.5 x 6.9 6.5 x 6.9 6.5 x 6.9 6.5 x 6.9 7.25 x 4.4 7.25 x 4.4 7.25 x 4.4 7 x 7.3 7 x 7.3 7 x 7.3 7 x 7.7 7 x 7.7 7.5 x 6.7 7.5 x 6.7 7.5 x 6.7 7.5 x 6.7 7.5 x 6.7 HEIGHT (mm) 3 3 3 3 3 3 3 3 3 3.0 3.0 3.0 3.8 3.8 3 3 3 3 3
Vishay IHLP-2525CZ-01
Sumida CDMC6D28 Series
Cooper HCP0703 Series
Wurth Electronik WE-HC744312 Series
Coilcraft SLC7530 Series
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LTC3614 APPLICATIONS INFORMATION
Output Capacitor (COUT ) Selection The selection of COUT is typically driven by the required ESR to minimize voltage ripple and load step transients (low ESR ceramic capacitors are discussed in the next section). Typically, once the ESR requirement is satisfied, the capacitance is adequate for filtering. The output ripple VOUT is determined by: 1 VOUT IL * ESR + 8 * fSW * COUT where fOSC = operating frequency, COUT = output capacitance and IL = ripple current in the inductor. The output ripple is highest at maximum input voltage since IL increases with input voltage. In surface mount applications, multiple capacitors may have to be paralleled to meet the capacitance, ESR or RMS current handling requirement of the application. Aluminum electrolytic, special polymer, ceramic and dry tantalum capacitors are all available in surface mount packages. Tantalum capacitors have the highest capacitance density, but can have higher ESR and must be surge tested for use in switching power supplies. Aluminum electrolytic capacitors have significantly higher ESR, but can often be used in extremely cost-sensitive applications provided that consideration is given to ripple current ratings and long-term reliability. Ceramic Input and Output Capacitors Ceramic capacitors have the lowest ESR and can be cost effective, but also have the lowest capacitance density, high voltage and temperature coefficients, and exhibit audible piezoelectric effects. In addition, the high Q of ceramic capacitors along with trace inductance can lead to significant ringing. They are attractive for switching regulator use because of their very low ESR, but great care must be taken when using only ceramic input and output capacitors. Ceramic capacitors are prone to temperature effects which require the designer to check loop stability over the operating temperature range. To minimize their large temperature and voltage coefficients, only X5R or X7R ceramic capacitors should be used. When a ceramic capacitor is used at the input and the power is being supplied through long wires, such as from a wall adapter, a load step at the output can induce ringing at the VIN pin. At best, this ringing can couple to the output and be mistaken as loop instability. At worst, the ringing at the input can be large enough to damage the part. Since the ESR of a ceramic capacitor is so low, the input and output capacitor must instead fulfill a charge storage requirement. During a load step, the output capacitor must instantaneously supply the current until the feedback loop raises the switch current enough to support the load. The time required for the feedback loop to respond is dependent on the compensation components and the output capacitor size. Typically, 3 to 4 cycles are required to respond to a load step, but only in the first cycle does the output drop linearly. The output droop, VDROOP , is usually about 2 to 4 times the linear drop of the first cycle; however, this behavior can vary depending on the compensation component values. Thus, a good place to start is with the output capacitor size of approximately: COUT 3.5 * IOUT fSW * VDROOP
This is only an approximation; more capacitance may be needed depending on the duty cycle and load step requirements. In most applications, the input capacitor is merely required to supply high frequency bypassing, since the impedance to the supply is very low.
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LTC3614 APPLICATIONS INFORMATION
Output Voltage Programming The output voltage is set by an external resistive divider according to the following equation: R1 VOUT = 0.6 * 1+ V R2 The resistive divider allows pin VFB to sense a fraction of the output voltage as shown in Figure 1. Burst Clamp Programming If the voltage on the MODE pin is less than 0.8V, Burst Mode operation is enabled. If the voltage on the MODE pin is less than 0.3V, the internal default burst clamp level is selected. The minimum voltage on the ITH pin is typically 525mV (internal clamp). If the voltage is between 0.45V and 0.8V, the voltage on the MODE pin (VBURST) is equal to the minimum voltage on the ITH pin (external clamp) and determines the burst clamp level IBURST (typically from 0A to 7A). When the ITH voltage falls below the internal (or external) clamp voltage, the sleep state is enabled. As the output load current drops, the peak inductor current decreases to keep the output voltage in regulation. When the output load current demands a peak inductor current that is less than IBURST , the burst clamp will force the peak inductor current to remain equal to IBURST regardless of further reductions in the load current. Since the average inductor current is greater than the output load current, the voltage on the ITH pin will decrease. When the ITH voltage drops, sleep mode is enabled in which both power switches are shut off along with most of the circuitry to minimize power consumption. All circuitry is turned back on and the power switches resume operation when the output voltage drops out of regulation. The value for IBURST is determined by the desired amount of output voltage ripple. As the value of IBURST increases, the sleep period between pulses and the output voltage ripple increase. Note that for very high VBURST voltage settings, the power good comparator may trip, since the output ripple may get bigger than the power good window. Pulse-skipping mode, which is a compromise between low output voltage ripple and efficiency, can be implemented by connecting MODE to SVIN. This sets IBURST to 0A. In this condition, the peak inductor current is limited by the minimum on-time of the current comparator. The lowest output voltage ripple is achieved while still operating discontinuously. During very light output loads, pulseskipping allows only a few switching cycles to skip while maintaining the output voltage in regulation. Internal and External Compensation The regulator loop response can be checked by looking at the load current transient response. Switching regulators take several cycles to respond to a step in DC load current. When a load step occurs, VOUT shifts by an amount equal to ILOAD(ESR), where ESR is the effective series resistance of COUT . ILOAD also begins to charge or discharge COUT , generating the feedback error signal that forces the regulator to adapt to the current change and return VOUT to its steady-state value. During this recovery time VOUT can be monitored for excessive overshoot or ringing, which would indicate a stability problem. The availability of the ITH pin allows the transient response to be optimized over a wide range of output capacitance. The ITH external components (RC and CC) shown in Figure 1 provide adequate compensation as a starting point for most applications. The values can be modified slightly to optimize transient response once the final PCB layout is done and the particular output capacitor type and value have been determined. The output capacitors need to be selected because the various types and values determine the loop gain and phase. The gain of the loop will be increased by increasing RC and the bandwidth of the loop will be increased by decreasing CC. If RC is increased by the same factor that CC is decreased, the zero frequency will be kept the same, thereby keeping the phase shift the same in the most critical frequency range of the feedback loop. The output voltage settling behavior is related to the stability of the closed-loop system. The external capacitor, CC1, (Figure 1) is not needed for loop stability, but it helps filter out any high frequency noise that may couple onto that node. The first circuit in the Typical Applications section uses faster compensation to improve step response.
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LTC3614 APPLICATIONS INFORMATION
A second, more severe transient is caused by switching in loads with large (>1F) supply bypass capacitors. The discharged bypass capacitors are effectively put in parallel with COUT , causing a rapid drop in VOUT . No regulator can alter its delivery of current quickly enough to prevent this sudden step change in output voltage if the load switch resistance is low and it is driven quickly. More output capacitance may be required depending on the duty cycle and load step requirements. AVP Mode Fast load transient response, limited board space and low cost are typical requirements of microprocessor power supplies. A microprocessor will typically exhibit full load steps with very fast slew rate. The voltage at the microprocessor must be held to about 0.1V of nominal in spite of these load current steps. Since the control loop cannot respond this fast, the output capacitors must supply the load current until the control loop can respond. Normally, several capacitors in parallel are required to meet microprocessor transient requirements. Capacitor ESR and ESL primarily determine the amount of droop or overshoot in the output voltage. Consider the LTC3614 without AVP with a bank of tantalum output capacitors. If a load step with very fast slew rate occurs, the voltage excursion will be seen in both directions, for full load to minimum load transient and for the minimum load to full load transient. If the ITH pin is tied to SVIN, the active voltage positioning (AVP) mode and internal compensation are selected. AVP mode intentionally compromises load regulation by reducing the gain of the feedback circuit, resulting in an output voltage that slightly varies with load current. When the load current suddenly increases, the output voltage starts from a level slightly higher than nominal so the output voltage can droop more and stay within the specified voltage range. When the load current suddenly decreases the output voltage starts at a level lower than nominal so the output voltage can have more overshoot and stay within the specified voltage range (see Figures 3 and 4). The benefit is a lower peak-to-peak output voltage deviation for a given load step without having to increase the output filter capacitance. Alternatively, the output voltage filter capacitance can be reduced while maintaining the same peak to peak transient response. Due to the reduced loop gain in AVP mode, no external compensation is required.
VOUT 200mV/DIV
VOUT 100mV/DIV
IL 1A/DIV 50s/DIV VIN = 3.3V VOUT = 1.8V ILOAD = 100mA TO 3A VMODE = 1.5V COMPENSATION FIGURE 1
3614 F03
IL 1A/DIV
50s/DIV VIN = 3.3V VOUT = 1.8V ILOAD = 100mA TO 3A VMODE = 1.5V VITH = 3.3V OUTPUT CAPACITOR VALUE FIGURE 1
3614 F04
Figure 3. Load Step Transient Forced Continuous Mode (AVP Inactive)
Figure 4. Load Step Transient Forced Continuous Mode with AVP Mode
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LTC3614 APPLICATIONS INFORMATION
DDR Mode The LTC3614 can both source and sink current if the MODE pin is configured to forced continuous mode. Current sinking is typically limited to 3A for 1MHz frequency and a 0.47H inductor, but can be lower at higher frequencies and low output voltages. If higher ripple current can be tolerated, smaller inductor values can increase the sink current limit. See the Typical Performance Characteristics curves for more information. In addition, by tying the SRLIM/DDR pin to SVIN, lower external reference voltage and tracking output voltage are possible. See the Output Voltage Tracking and External Reference Input sections. Soft-Start The RUN pin provides a means to shut down the LTC3614. Tying the RUN pin to SGND places the LTC3614 in a low quiescent current shutdown state (IQ < 1A). When the LTC3614 is enabled by pulling the RUN pin high, the chip enters a soft start-up state. The type of soft startup behavior is set by the TRACK/SS pin: 1. Tying TRACK/SS to SVIN selects the internal soft-start circuit. This circuit ramps the output voltage to the final value within 1ms. 2. If a longer soft-start period is desired, it can be set externally with a resistor and capacitor on the TRACK/SS pin as shown in Figure 1. The TRACK/SS pin reduces the value of the internal reference at VFB until TRACK/SS is pulled above 0.6V. The external soft-start duration can be calculated by using the following formula: SVIN t SS = RSS * CSS * ln SVIN - 0.6V 3. The TRACK/SS pin can be used to track the output voltage of another supply. Each time the RUN pin is tied high and the LTC3614 is turned on, the TRACK/SS pin is internally pulled down for ten microseconds in order to discharge the external capacitor. This discharging time is typically adequate for capacitors up to about 33nF If a larger capacitor is . required, connect the external soft-start resistor to the RUN pin. During either internal or external soft-start, the MODE pin is ignored and soft-start will always be in pulse-skipping mode. In addition, the PGOOD pin is kept low and foldback of the switching frequency is disabled. Programmable Switch Pin Slew Rate As switching frequencies rise, it is desirable to minimize the transition time required when switching to minimize power losses and blanking time for the switch to settle. However, fast slewing of the switch node results in relatively high external radiated EMI and high on chip supply transients, which can cause problems for some applications.
SW PIN
SW PIN
10k 100k OPEN
OPEN 100k 10k
VIN = 3.3V VOUT = 1.8V fSW = 2.25MHz
2ns/DIV
VIN = 3.3V VOUT = 1.8V fSW = 2.25MHz
2ns/DIV
3614 F05
Figure 5. Slew Rate at SW Pin vs SRLIM/DDR Resistor: Open, 100k, 10k
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LTC3614 APPLICATIONS INFORMATION
The LTC3614 allows the user to control the slew rate of the switching node SW by using the SRLIM/DDR pin. Tying this pin to ground selects the fastest slew rate. The slowest slew rate is selected when the pin is open. Connecting a resistor (between 10k and 100k) from SRLIM pin to ground adjusts the slew rate between the maximum and minimum values. The reduced dV/dt of the switch node results in a significant reduction of the supply and ground ringing, as well as lower radiated EMI. Particular attention should be used with very high switching frequencies. Using the slowest slew rate (SRLIM open) can reduce the minimum duty cycle capability. Output Voltage Tracking Input If the DDR pin is not tied to SVIN, once VTRACK/SS exceeds 0.6V, the run state is entered and the MODE selection, power good and current foldback circuits are enabled. In the run state, the TRACK/SS pin can be used for tracking down/up the output voltage of another supply. If the VTRACK/SS drops below 0.6V, the LTC3614 enters the down tracking state and VOUT is referenced to the TRACK/SS voltage. If the TRACK/SS pin drops below 0.2V, the switching frequency is reduced to ensure that the minimum duty cycle limit does not prevent the output from following the TRACK/SS pin. The run state will resume if VTRACK/SS again exceeds 0.6V and VOUT is referenced to the internal precision reference (see Figure 8). Through the TRACK/SS pin, the output voltage can be set up for either coincident or ratiometric tracking, as shown in Figure 6. To implement the coincident tracking behavior in Figure 6a, connect an extra resistive divider to the output of the master channel and connect its midpoint to the TRACK/SS pin for the slave channel. The ratio of this divider should be selected to be the same as that of the slave channel's feedback divider (Figure 7a). In this tracking mode, the master channel's output must be set higher than slave channel's output. To implement the ratiometric tracking behavior in Figure 6b, different resistor divider values must be used as specified in Figure 7b.
OUTPUT VOLTAGE VOUT1 OUTPUT VOLTAGE
VOUT2
TIME
(6a) Coincident Tracking
VOUT1
VOUT2
3614 F06
TIME
(6b) Ratiometric Tracking
Figure 6. Two Different Modes of Output Voltage Tracking
VOUT1
VOUT2 R4 VFB2 R2 LTC3614 TRACK/SS2
R4
R3 VFB1 VIN
R2
R2
LTC3614 TRACK/SS1
R4 R3 LTC3614 CHANNEL 2 SLAVE LTC3614 CHANNEL 1 MASTER
3614 F07a
Figure 7a. Setup for Coincident Tracking
VOUT2 R1 VFB2 R2 LTC3614 TRACK/SS2 LTC3614 CHANNEL 2 SLAVE R6 R4 VOUT1
R5
R3 R1/R2 < R5/R6 VFB1 LTC3614 TRACK/SS1 VIN
LTC3614 CHANNEL 1 3614 F07b MASTER
Figure 7b. Setup for Ratiometric Tracking
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LTC3614 APPLICATIONS INFORMATION
For coincident start-up, the voltage value at the TRACK/SS pin for the slave channel needs to reach the final reference value after the internal soft-start time (around 1ms). The master start-up time needs to be adjusted with an external capacitor and resistor to ensure this. External Reference Input (DDR Mode) If the DDR pin is tied to SVIN (DDR mode), the run state is entered when VTRACK/SS exceeds 0.3V and tracking down behavior is possible if the VTRACK/SS voltage is below 0.6V. This allows TRACK/SS to be used as an external reference between 0.3V and 0.6V if desired. During the run state in DDR mode, the power good window moves in relation to the actual TRACK/SS pin voltage if the voltage value is between 0.3V and 0.6V. Note: if TRACK/SS voltage is 0.6V, either the tracking circuit or the internal reference can be used. During up/down tracking the output current foldback is disabled and the PGOOD pin is always pulled down (see Figure 9). Efficiency Considerations The efficiency of a switching regulator is equal to the output power divided by the input power times 100%. It is often useful to analyze individual losses to determine what is limiting the efficiency and which change would produce the most improvement. Efficiency can be expressed as: Efficiency = 100% - (L1 + L2 + L3 + ...) where L1, L2, etc. are the individual losses as a percentage of input power. Although all dissipative elements in the circuit produce losses, two main sources usually account for most of the losses: VIN quiescent current and I2R losses. The VIN quiescent current loss dominates the efficiency loss at very low load currents whereas the I2R loss dominates the efficiency loss at medium to high load currents. In a typical efficiency plot, the efficiency curve at very low load currents can be misleading since the actual power lost is usually of no consequence. 1. The VIN quiescent current is due to two components: the DC bias current as given in the Electrical Characteristics and the internal main switch and synchronous switch gate charge currents. The gate charge current results from switching the gate capacitance of the internal power MOSFET switches. Each time the gate is switched from low to high to low again, a packet of charge dQ moves from VIN to ground. The resulting dQ/dt is the current out of VIN due to gate charge, and it is typically larger than the DC bias current. Both the DC bias and gate charge losses are proportional to VIN; thus, their effects will be more pronounced at higher supply voltages. 2. I2R losses are calculated from the resistances of the internal switches, RSW , and external inductor, RL. In continuous mode the average output current flowing through inductor L is "chopped" between the main switch and the synchronous switch. Thus, the series resistance looking into the SW pin is a function of both top and bottom MOSFET RDS(ON) and the duty cycle (DC) as follows: RSW = (RDS(ON)TOP)(DC) + (RDS(ON)BOT)(1 - DC) The RDS(ON) for both the top and bottom MOSFETs can be obtained from the Typical Performance Characteristics curves. To obtain I2R losses, simply add RSW to RL and multiply the result by the square of the average output current. Other losses including CIN and COUT ESR dissipative losses and inductor core losses generally account for less than 2% of the total loss.
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LTC3614 APPLICATIONS INFORMATION
VFB PIN 0.6V VOLTAGE 0V
0.6V TRACK/SS PIN VOLTAGE 0.2V 0V VIN 0V VIN 0V TIME SHUTDOWN SOFT-START STATE STATE tSS > 1ms RUN STATE REDUCED SWITCHING FREQUENCY DOWN TRACKING STATE UP TRACKING STATE RUN STATE
3614 F08
RUN PIN VOLTAGE
SVIN PIN VOLTAGE
Figure 8. DDR Pin Not Tied to SVIN
0.45V VFB PIN 0.3V VOLTAGE 0V
0.45V TRACK/SS 0.3V PIN VOLTAGE 0.2V 0V VIN RUN PIN VOLTAGE 0V VIN 0V
EXTERNAL VOLTAGE REFERENCE 0.45V
SVIN PIN VOLTAGE
TIME SHUTDOWN SOFT-START STATE STATE tSS > 1ms RUN STATE REDUCED SWITCHING FREQUENCY DOWN TRACKING STATE UP TRACKING STATE RUN STATE
3614 F09
Figure 9. DDR Pin Tied to SVIN. Example DDR Application
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LTC3614 APPLICATIONS INFORMATION
Thermal Considerations In most applications, the LTC3614 does not dissipate much heat due to its high efficiency. However, in applications where the LTC3614 is running at high ambient temperature with low supply voltage and high duty cycles, such as in dropout, the heat dissipated may exceed the maximum junction temperature of the part. If the junction temperature reaches approximately 160C, both power switches will be turned off and the SW node will become high impedance. To prevent the LTC3614 from exceeding the maximum junction temperature, some thermal analysis is required. The temperature rise is given by: TRISE = (PD)(JA) where PD is the power dissipated by the regulator and JA is the thermal resistance from the junction of the die to the ambient temperature. The junction temperature, TJ, is given by: TJ = TA + TRISE where TA is the ambient temperature. As an example, consider the case when the LTC3614 is in dropout at an input voltage of 3.3V with a load current of 4A at an ambient temperature of 85C. From the Typical Performance Characteristics graph of Switch Resistance, the RDS(ON) resistance of the P-channel switch is 0.038. Therefore, power dissipated by the part is: PD = (IOUT)2 * RDS(ON) = 0.61W For the QFN package, the JA is 38C/W. Therefore, the junction temperature of the regulator operating at 85C ambient temperature is approximately: TJ = 0.61W * 38C/W + 85C = 108C We can safely assume that the actual junction temperature will not exceed the absolute maximum junction temperature of 125C. Note that for very low input voltage, the junction temperature will be higher due to increased switch resistance, RDS(ON). It is not recommended to use full load current with high ambient temperature and low input voltage. To maximize the thermal performance of the LTC3614 the exposed pad should be soldered to a ground plane. See the PCB Layout Board Checklist.
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LTC3614 PACKAGE DESCRIPTION
Design Example As a design example, consider using the LTC3614 in an application with the following specifications: VIN = 2.25V to 5.5V, VOUT = 1.8V, IOUT(MAX) = 4A, IOUT(MIN) = 200mA, f = 2.6MHz. Efficiency is important at both high and low load current, so Burst Mode operation will be utilized. First, calculate the timing resistor: 3.8211Hz RT = k - 16k = 130k 2.6MHz Next, calculate the inductor value for about 33% ripple current at maximum VIN: 1.8V 1.8V L= * 1- = 0.35H 2.6MHz * 1.3A 5.5V Using a standard value of 0.33H inductor results in a maximum ripple current of: 1.8V 1.8V IL = * 1- = 1.41A 2.6MHz * 0.33H 5.5V COUT will be selected based on the ESR that is required to satisfy the output voltage ripple requirement and the bulk capacitance needed for loop stability. For this design, a 100F ceramic capacitor is used with a X5R or X7R dielectric. Assuming worst-case conditions of VIN = 2VOUT, CIN should be selected for a maximum current rating of: IRMS = 4A * 1.8V 3.6V * - 1 = 2ARMS 1.8V 3.6V The standard value of 22nF guarantees the minimum soft-start up time of 5ms. Figure 1 shows the schematic for this design example. PC Board Layout Checklist When laying out the printed circuit board, the following checklist should be used to ensure proper operation of the LTC3614: 1. A ground plane is recommended. If a ground plane layer is not used, the signal and power grounds should be segregated with all small-signal components returning to the SGND pin at one point which is then connected to the PGND pin close to the LTC3614. 2. Connect the (+) terminal of the input capacitor(s), CIN, as close as possible to the PVIN pin, and the (-) terminal as close as possible to the exposed pad, PGND. This capacitor provides the AC current into the internal power MOSFETs. 3. Keep the switching node, SW, away from all sensitive small-signal nodes. 4. Flood all unused areas on all layers with copper. Flooding with copper will reduce the temperature rise of power components. Connect the copper areas to PGND (exposed pad) for best performance. 5. Connect the VFB pin directly to the feedback resistors. The resistor divider must be connected between VOUT and SGND. Finally, define the soft start-up time choosing the proper value for the capacitor and the resistor connected to TRACK/SS. If we set minimum tSS = 5ms and a resistor of 2M, the following equation can be solved with the maximum SVIN = 5.5V : CSS = 5ms = 21.6nF 5.5V 2M *In 5.5V - 0.6V
Decoupling PVIN with four 10F to 22F capacitors is adequate for most applications. If we set R2 = 196k, the value of R1 can now be determined by solving the following equation. 1.8V R1 = 196k * -1 0.6V A value of 392k will be selected for R1.
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24
LTC3614 TYPICAL APPLICATIONS
General Purpose Buck Regulator with Fast Compensation and Improved Step Response, 2.25MHz
VIN 2.25V TO 5.5V 10F 4 RF 24 CF 1F
RSS 4.7M CSS 10nF RC 43k CC 220pF CC1 10pF PGOOD R5A 1M R5B 1M L1: VISHAY IHLP-2525CZ-01 330nH
R4 100k
SVIN PVIN RUN TRACK/SS SRLIM/DDR RT/SYNC LTC3614 SW PGOOD SGND ITH PGND MODE VFB R2 196k
L1 0.33H CO2 100F R1 392k C3 22pF
3614 TA02a
VOUT 1.8V 4A
Efficiency vs Output Current
100 90 80 EFFICIENCY (%) 70 60 50 40 30 20 10 0 1 VIN = 2.5V VIN = 3.3V VIN = 4V VIN = 5.5V 10 100 1000 OUTPUT CURRENT (mA) 10000
3614 TA02b
Load Step Response in Forced Continuous Mode
VOUT = 1.8V VOUT 100mV/DIV
IOUT 2A/DIV 50s/DIV VIN = 3.3V VOUT = 1.8V IOUT = 100mA TO 4A VMODE = 1.5V
3614 TA02c
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25
LTC3614 TYPICAL APPLICATIONS
Master and Slave for Coincident Tracking Outputs Using a 1MHz External Clock
VIN 2.25V TO 5.5V 22F 4 RF1 24 CF1 1F
4.7M 10nF
1MHz CLOCK RC1 15k CC1 470pF CC2 10pF 1M R5 100k PGOOD
SVIN PVIN RUN TRACK/SS SRLIM/DDR RT/SYNC LTC3614 SW PGOOD SGND ITH PGND MODE VFB R2 357k
L1 0.68H
CHANNEL 1 MASTER VOUT1 1.8V 4A
CO12 100F R1 715k C3 22pF R3 464k R4 464k
1M
22F 4
RF2 24 CF2 1F
RC2 15k CC3 470pF CC4 10pF
R7 100k PGOOD
SVIN PVIN RUN TRACK/SS SRLIM/DDR RT/SYNC LTC3614 SW PGOOD SGND ITH PGND MODE VFB R6 301k
CHANNEL 2 SLAVE L2 0.68H VOUT2 1.2V CO22 4A 100F
R5 301k C7 22pF
3614 TA03a
L1, L2: VISHAY IHLP-2525CZ-01 680nH
Coincident Start-Up
Coincident Tracking Up/Down
VOUT1 VOUT2 500mV/DIV 500mV/DIV VOUT1 VOUT2
2ms/DIV
3614 TA03b
200ms/DIV
3614 TA03c
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26
LTC3614 PACKAGE DESCRIPTION
UDD Package 24-Lead Plastic QFN (3mm x 5mm)
(Reference LTC DWG # 05-08-1833)
0.70 0.05 3.50 0.05 2.10 0.05 1.50 REF
3.65 0.05 1.65 0.05
PACKAGE OUTLINE 0.25 0.05 0.50 BSC 3.50 REF 4.10 0.05 5.50 0.05 RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 0.75 0.05 3.00 0.10 R = 0.05 TYP 1.50 REF 23
PIN 1 NOTCH R = 0.20 OR 0.25 45 CHAMFER 24 0.40 0.10
PIN 1 TOP MARK (NOTE 6) 3.65 0.10 5.00 0.10 3.50 REF 1.65 0.10
1 2
(UDD24) QFN 0808 REV O
0.200 REF 0.00 - 0.05
R = 0.115 TYP
0.25 0.05 0.50 BSC
BOTTOM VIEW--EXPOSED PAD NOTE: 1. DRAWING IS NOT A JEDEC PACKAGE OUTLINE 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE
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Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
27
LTC3614 TYPICAL APPLICATION
DDR Termination With Ratiometric Tracking of VDD, 1MHz
VIN 3.3V
Ratiometric Start-Up
VDD
C1 22F 4 R6 562k R7 187k PGOOD RC 6k R4 1M R5 1M CC 2.2nF CC1 10pF R3 100k
VDD 1.8V
R8 365k
SVIN RUN TRACK/SS RT/SYNC
PVIN SRLIM/DDR L1 0.33H SW SGND PGND VFB R2 200k R1 200k C3 22pF
3614 TA04a
500mV/DIV
VTT
LTC3614 PGOOD
C4 100F
VTT 0.9V C5 3A 47F
500s/DIV
3614 TA04b
ITH MODE
L1: COILCRAFT DO3316T
RELATED PARTS
PART NUMBER LTC3616 LTC3612 LTC3418 LTC3415 LTC3416 LTC3413 LTC3412A DESCRIPTION 5.5V, 6A (IOUT) 4MHz Synchronous Step-Down DC/DC Converter 5.5V, 3A (IOUT), 4MHz, Synchronous Step-Down DC/DC Converter 5.5V, 8A (IOUT), 4MHz, Synchronous Step-Down DC/DC Converter 5.5V, 7A (IOUT), 1.5MHz, Synchronous Step-Down DC/DC Converter 5.5V, 4A (IOUT), 4MHz, Synchronous Step-Down DC/DC Converter 5.5V, 3A (IOUT Sink/Source), 2MHz, Monolithic Synchronous Regulator for DDR/QDR Memory Termination 5.5V, 2.5A (IOUT), 4MHz, Synchronous Step-Down DC/DC Converter COMMENTS 95% Efficiency, VIN(MIN) = 2.25V, VIN(MAX) = 5.5V, VOUT(MIN) = 0.6V, IQ = 70A, ISD < 1A, 3mm x 5mm QFN24 Package 95% Efficiency, VIN(MIN) = 2.25V, VIN(MAX) = 5.5V, VOUT(MIN) = 0.6V, IQ = 70A, ISD <1A, 3mm x 4mm QFN-20 TSSOP20E Package 95% Efficiency, VIN(MIN) = 2.25V, VIN(MAX) = 5.5V, VOUT(MIN) = 0.8V, IQ = 380A, ISD <1A, 5mm x 7mm QFN-38 Package 95% Efficiency, VIN(MIN) = 2.5V, VIN(MAX) = 5.5V, VOUT(MIN) = 0.6V, IQ = 450A, ISD <1A, 5mm x 7mm QFN-38 Package 95% Efficiency, VIN(MIN) = 2.25V, VIN(MAX) = 5.5V, VOUT(MIN) = 0.8V, IQ = 64A, ISD <1A, TSSOP20E Package 90% Efficiency, VIN(MIN) = 2.25V, VIN(MAX) = 5.5V, VOUT(MIN) = VREF /2, IQ = 280A, ISD <1A, TSSOP16E Package 95% Efficiency, VIN(MIN) = 2.5V, VIN(MAX) = 5.5V, VOUT(MIN) = 0.8V, IQ = 60A, ISD <1A, 4mm x 4mm QFN-16 TSSOP16E Package
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28 Linear Technology Corporation
(408) 432-1900
LT 0310 * PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
FAX: (408) 434-0507 www.linear.com
(c) LINEAR TECHNOLOGY CORPORATION 2010

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